Basic Infomation
Teachers: wht, ll
Lab Docs: 浙江大学24年春夏系统贯通一实验( ZJU intranet required )
Because of some reasons, Chapter 04 should change position with Chapter 05
Chapter 09 Combination Logic
Introduction to Verilog HDL
What is HDL (Hardware Description Language)?
VHDL, Verilog, SystemC, SystemVerilog, C/C++, …
Logical design with HDL -> Simulation -> Synthesis -> Phyiscal design-> Final steps
C++ 学过吗？（没有）Java 学过吗？（没有）Python 学过吗？（没有）ok…
Modeling Methods
Combination Logic Circuit
A Type of Digital Logic Circuit
- inputs
- outputs
Combination vs. Sequential Circuits
Characteristics
- Each element is a comb. circuit
- A node cannot be the output of 2 element
- Loop is banned
Design Choice
Some Classic / Basic Designs
Encoder & Decoder
Multiplexer & Demultiplexer
Half adder & full adder
为什么理论课的东西会落后实验课这么多呢
Timing Analysis
: max time delay
: min time delay
Chapter 10 Sequential Logic
Introduction to Sequential Circuits
Bistable Circuits
Latch
Flip-Flop
锁存器 & 触发器
Types of Sequential Circuits
- Synchronous
- Asynchronous
Finite State Machine & State Diagram
State Table
Basic Sequential Logic Elements
- Latches
- Flip Flop
Bistable Circuit
SR Latch (with NOR Gates)
一级逻辑门电路会消耗几纳秒
Latch (with NAND Gates)
D Latch (Data Latch)
Avoid invalid case
The Latch Timing Problem
Solution: master-slave flip-flop
- Edge-triggered flip-flop
- Pulse-triggered flip-flop
Pulse-triggered Flip-Flop
Edge-triggered D Flip-Flop
JK Flip-Flop
[Figure]
T Flip-Flop
[Figure]